1. Field of the Invention
The present invention relates to a non-volatile memory cell structure, and more particularly, to a flash memory cell structure and an operating method thereof.
2. Description of the Prior Art
Refer to FIG. 1. A prior art flash memory cell structure 1 includes a substrate 10, a drain 11, a source 12, two field oxidation layers 13, a control gate 14, a floating gate 15, and a P well 16. The drain 11 and the source 12 are formed in the substrate 10 and between the field oxidation layers 13. A stacked gate, which includes the control gate 14 and the floating gate 15, is between the drain 11 and the source 12. Further, the P well 16 is implanted around the drain 11 and the source 12. As shown in FIG. 1, a gate voltage VG is applied to the control gate 14 for controlling the flash memory cell structure 1, and the floating gate 15 is floating. When the programming process is executed, the gate voltage VG is 9V, the drain voltage VD applied to the drain 11 is 6V, the source voltage VS is floating, and the base voltage VB applied to the substrate 10 is 0V. In this case, electrons (e−) located in the floating gate 15 will be emitted to the drain 11 due to edge Fowler-Nordheim effect, such that the flash memory cell structure 1 is programmed. When the drain voltage VD is applied to the drain 11, however, a depletion region will be formed outside the drain 11 and therefore hot holes (e+) will be generated. In that case, the lateral electric field will result in hot hole injection, and will seriously affect normal operation of the flash memory cell structure 1.
In view of the above-mentioned shortcomings, the prior art provides an improved flash memory cell structure and operating method thereof. Refer to FIG. 2, the drain 11 and the P well 16 are electrically short-circuited together and are applied with an identical voltage, such as 6V. In that case, the flash memory cell structure operates under the channel Fowler-Nordheim effect, and thus the depletion region will not be generated in the junction between the drain 11 and the P well 16, and neither will be the hot holes.
Although employing the channel Fowler-Nordheim effect in the foregoing flash memory cell structure can overcome drawbacks, this may result in other problems. Though the drain 11 and the P well 16 are electrically short-circuited together, the P well 16, however, extends into the substrate 10 Therefore the neighboring source 12 could be influenced, and further the operation of adjacent flash memory cell structures could be affected.
To avoid the adjacent source being affected because of the electrical connection of the drain 11 and the P well 16, another flash memory cell structure 2 is disclosed in U.S. Pat. No. 6,091,644. As shown in FIG. 3, the flash memory cell structure 2 includes a substrate 20, a first-type doped region 25, a shallow second-type doped region 26, a deep second-type doped region 27, and a doped source region 28. The substrate 25 includes a field oxidation layer 21 and a stacked gate. The field oxidation layer 21 has a channel stop 22 below. The stacked gate includes a control gate 23 and a floating gate 24. In the flash memory cell structure 2, the first-type doped region 25 is a drain, the deep second-type doped region 27 is a P well, and the doped source region 28 is a source. Each drain corresponds to a P well, and thus, operation of adjacent source and flash memory cell structure will not be influenced even if the drain and the P well are electrically short-circuited together.
Nevertheless, the drain and the P well are electrically short-circuited in the flash memory cell structure 2, thus the P well will have the same voltage potential as the drain when programming. Meanwhile, the adjacent flash memory cell structure to be programmed (not shown) is given the same gate voltage potential as the flash memory cell structure 2, so an edge program disturb issue will occur. For avoiding the edge program disturb issue, the prior art thickens the tunnel oxide layer on the edge of the floating gate. However, it is not easy to control the thickness in the manufacturing process, and the reliability will be further reduced. Furthermore, the flash memory cell structure adjacent to the flash memory cell structure 2 has leakage problems when the flash memory cell structure 2 is programmed. Generally speaking, those skilled in the art apply a specific voltage, such as 2V, to the control gate of the adjacent flash memory cell structure to overcome the leakage problem during programming. If a negative voltage is not applied, the charging pumping will increase, which could further cause a malfunction of the flash memory cell structure.
Therefore, a flash memory cell structure, which counters the edge program disturb issue, diminishes the over program problem, and reduces current leakage becomes desirable.